Design of Approximate Digital Circuits on Advanced Semiconductor Technologies

This thesis investigates the design of approximate digital circuits with Gaussian error distributions, primarily targeting, but not limited to, Post Quantum Cryptography (PQC) applications. The growing importance of PQC in secure communications highlights the need for efficient and reliable arithmetic circuits. The primary objective of this research is to develop an architecture that integrates Gaussian noise directly into the design of an approx- imate adder, thus eliminating the need for external noise sources. Existing architectures of approximate adders in the literature primarily focus on sacrificing accuracy for efficiency, such as in area, power consumption or clock frequency, rather than on controlling the error distribution. To address this gap, a novel structure, called Approximator, was developed, along with a method to derive its architecture based on the desired standard deviation. The design em- ploys bit-flipping mechanisms in the Least Significant Bits (LSBs) of the arithmetic circuit to generate Gaussian errors. The Approximator can be applied to different arithmetic circuits to approximate them with a Gaussian error distribution with zero mean and any standard deviation. This thesis demonstrates that the proposed architecture effectively generates Gaussian- distributed errors within the circuit, maintaining the error distribution without relying on external noise sources, thereby reducing area and power consumption. These findings make a significant contribution to the field of approximate computing, particularly in PQC appli- cations. Future work will focus on the physical implementation of the design, assessing the impact of input-error correlation on overall system performance, and exploring the potential to generate other types of error distributions.