Towards Scalable Silicon Qubits: TCAD Simulations of Gate-Defined Single-Electron Transistors

Many options have been proposed to physically implement qubits (the fundamental information units of quantum computers) including well-known solutions such as superconducting qubits, trapped ions, and photonic qubits, as well as more research-level implementations like neutral atom-based qubits. Among these, silicon quantum dot-based qubits are considered one of the most promising alternatives, thanks to the relatively long coherence times associated with the weak interaction between electron spins and the silicon crystal lattice, as well as their compatibility with CMOS manufacturing processes and potential scalability. This latter advantage allows the use of well-established and optimized industrial manufacturing processes to scale up and integrate multiple physical qubits into a single chip, enabling the encoding of logical qubits to improve robustness against decoherence. A key element in silicon qubit platforms are gate-defined Single-Electron Transistors (SETs), used for single-shot readout of spin qubit states through the spin-to-charge conversion mechanism. At the Institute of Microelectronics of Barcelona (IMB-CNM, CSIC), two different device architectures are currently under fabrication: a planar MOSFET-like structure built on bulk silicon, and a nanowire-based Single Electron Transistor (SET) fabricated on a Silicon-On-Insulator (SOI) wafer. This Thesis aims to study the behavior of these devices—fabricated using IMB-CNM facilities—through TCAD simulations. Simulations were performed using Synopsys 3D TCAD Sentaurus software, with the goal of predicting the behavior of the devices under development, providing a better understanding of their physics, and offering physical insights that can help interpret experimental measurements. A semi-classical model was employed, solving carrier continuity equations for electrons and holes alongside the Poisson equation via a Newton-like solver. The simulations incorporated Fermi-Dirac statistics and accounted for incomplete ionization of dopants. To improve convergence at cryogenic temperatures, we adopted the hydrodynamic transport model with a quasi-stationary temperature ramp. The tunneling rate was computed using the WKB approximation. Low-temperature simulations, down to T = 20 K, are carried out to investigate how device behavior changes with temperature, since the operating regime of SETs in silicon qubit platforms lies in the millikelvin range, in order to suppress thermionic current noise and limit spin decoherence due to interactions with the surrounding environment. The fabrication processes are described, and the simulation results are compared with both literature data and the initial electrical measurements of the fabricated devices. The simulation results show good agreement with those reported in the literature. Although the model used is semi-classical and not sophisticated enough to capture single-electron effects such as Coulomb blockade, it can be adapted for further studies to simulate different device configurations, allowing for detailed analysis of geometry and material-related effects.