Efficient Compaction and Compression Algorithms for Diagnostic Data from Tests of Memories Embedded in Automotive System-on-Chips

The modern automotive industry makes great use of System-on-Chips (SoCs) in their products. One very relevant component present inside of the SoCs is the integrated random access memory. These memories are characterized by a probability of failure graph, which can be expressed using the Bathtub Curve. After the “packaging” of the SoC is carried out a process called “burn-in” is performed. This procedure consists of a certain number of reading and writing cycles on the memory, these cycles are repeated for a sufficient amount of time to bring the memories out of the “Infant Mortality” region. At the end of this process the SoCs that present some failures inside their memories, can either be repaired or either be discarded. During these procedures, having the ability to keep track of failures within the memory is very important. This operation must be performed entirely on the SoC, mainly driven by timing advantage, because acting on the system externally will consume a significant amount of time. The stored faults will be used for chip repair strategies or for later data analysis. The Sub-Line Aggregation and Coloring (SLAC) is an algorithm that is capable of performing on-chip computation, storing the data using a compression algorithm. At the end of the entire test-flow the data can be extracted, allowing further analysis. The algorithm stores the faults inside the memory using shape-like objects, these shapes are called slices. Every slice is an oriented-memory-interval which represent a set of cells where the memory failed. The memories will usually have failures along bit-lines or word-lines, usually due to physical defects, creating a compact distribution of faults. The main topic of this thesis will be an extension of the SLAC algorithm called Delta-SLAC algorithm. The aim is to reduce the memory occupation of the SLAC. The concept behind the idea of the algorithm follows an empirical observation about memory failures, some of the failures arise due to physical defects inside the design, those bits remain stuck in their state which can be a logical ′0′ or ′1′, these are called stuck-at faults. During a test-flow the memory can be written and read multiple times, during each read operation the memory-state will be saved. If stuck-at faults are present, their information will be repeated for every executed test. The Delta-SLAC algorithm aims to keep track of the differences in the memory-state from test to test, only storing the symmetric-difference between different two subsequent test, if an information is repeated between two tests it will not be stored. The Delta-SLAC achieves the maximum memory-efficiency by also keeping track of the different patterns that the memory has been written with. If these distinctions where not mode, more memory than necessary would be used. In order to obviate this problem, the first two patterns will be the set-up patterns, these will result in two bases to compute the following deltas. Upon the reading of a specific written pattern, the difference will be computed accordingly, filtering out the faults that should not be present in the current pattern. Some statistical analysis has been performed to verify the efficiency of the algorithm, the used data comes from a real production environment. The algorithm was tested on real SoCs, where the faults, coming from previously registered test-flows, where used to perform the analysis and the validation of the algorithm. In all of the analyzed cases the algorithm saves memory, with a maximum of 95%.