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Evaluating Hardware Offload of Network Functions with SmartNICs

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Evaluating Hardware Offload of Network Functions with SmartNICs.

Rel. Fulvio Giovanni Ottavio Risso, Davide Miola. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2025

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Abstract:

The increasing demand for efficient and scalable data center networks has led the industry to the exploration of hardware acceleration technologies, which allow to offload portions of the Linux network stack processing away from the main CPUs and into dedicated accelerators such as SmartNICs, thereby promising advancements in overall system performance and efficiency. This thesis questions these claims by conducting a series of experiments to evaluate the performance and efficiency gains achieved by adopting NVIDIA ConnectX-7 100Gbps SmartNICs across several server configurations. The tests covered a variety of networking scenarios, including encapsulation, IPsec encryption, and the deployment of real world cloud-native applications within a Kubernetes cluster. Results indicate that SmartNICs can significantly reduce CPU overhead for IPsec encryption tasks. However, in other cases, improvements were only measurable on older and less powerful processors, while more modern hardware showed limited benefits.

Relatori: Fulvio Giovanni Ottavio Risso, Davide Miola
Anno accademico: 2024/25
Tipo di pubblicazione: Elettronica
Numero di pagine: 61
Soggetti:
Corso di laurea: Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering)
Classe di laurea: Nuovo ordinamento > Laurea magistrale > LM-32 - INGEGNERIA INFORMATICA
Aziende collaboratrici: NON SPECIFICATO
URI: http://webthesis.biblio.polito.it/id/eprint/35472
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