Hardware design of a high bit rate decoding chain for a full digital ASK demodulator in Wireless Power Transfer application

The thesis work consisted of the analysis and design of a fully digital ASK demodulator integrated within a wireless power transmitter system. The activity was done during an internship at STMicroelectronics, carried out at the Catania site with the digital competency center group in the General Purpose and Custom Analog Division, aiming to provide digital design solutions in mixed-signal systems. A fully digital system was chosen for its simplicity and cost-effectiveness compared to analog, and for its superior processing power, enabling higher wireless transmission bit rates. The digital ASK demodulator architecture from STMicroelectronics was conceived with two main sub-blocks: one responsible for the demodulation and the other for symbol decoding. In the first part of the chain, high data rate samples from the ADC are collected and the amplitude demodulation is performed. Then the signal is down-sampled to move to the second part of the chain where, with a lower data rate, information decoding is done. The focus was on enhancing symbol decoding of an existing IP while retaining the previous generation's demodulation sub-block. The first task of the work was the study of the already existing IP documentation and RTL code to understand the starting point of the new design. The second part of the thesis work involved re-designing the symbol decoding section of the chain with a different approach to the problem: while the existing IP symbol decoding was firmware-based, the new approach is more hardware-oriented, with the implementation of correlator filters tuned according to the bi-phase differential Manchester encoding scheme employed in the communication. The work included studying the theory behind the new symbol decoding approach: it involves correlators to recognize the expected pattern of bit '1', correlators over a multiple number of bits, peak detector analysis, PLL for sample decimation, multi-bit words score evaluation, maximum score analysis, and early detection to optimize the process. The design process began with the realization of a Matlab model of the system. This model was created starting from the golden one associated with the previous IP with the goal of defining a reference for the verification of the RTL code. The next step was the design and verification of each building block of the symbol decoding system in RTL using System Verilog. Each block was tested separately with real waveforms by providing the input of the corresponding samples of the Matlab model, while the outputs were compared with the equivalent results to verify the correct behavior of the RTL code. The blocks of the demodulation part of the chain were imported from the previous IP project and finally, everything was integrated together using Magillem tool from Arteris and tested to check overall functionality.