Custom RISC-V Processor Development in an FPGA Architecture for On-Board Computing in Space Applications

This thesis presents the design and implementation of a custom RISC-V core, which was developed as part of an internal research effort at Argotec, an Italian aerospace company. The primary objective of this work was to develop a RISC-V-based processor that could serve as a robust and flexible computing solution for future projects, particularly in the aerospace domain. The core was designed with an emphasis on providing a generic architecture that can be easily adapted and customized according to the specific requirements. ???? The implementation was based on the RV32I base version of the RISC-V instruction set architecture (ISA), which was selected for its simplicity and suitability for the targeted system. The processor was designed around a five-stage pipeline architecture, which allows for efficient instruction processing. The design process involved addressing several critical aspects of pipeline performance, including hazard handling, data dependencies, and branch and jump operations. The goal was not only to implement the core efficiently but also to ensure that the architecture could be easily extended and modified for various use cases in the future. ???? A key feature of the core’s design is its integration with external systems, which is facilitated through the use of AHB and APB buses. These buses provide the necessary interface for communication between the processor and external memory and peripherals. The core is equipped with essential peripherals, including a UART-based Commander Unit, which serves as programmer and debug unit of the processor. The design also included the creation of a custom C compiler to facilitate the execution of programs on the core, ensuring that the software could take full advantage of the processor's capabilities while remaining flexible for future optimizations. ???? The design was tested on an FPGA platform, which provided a practical environment for verifying the functionality of the processor and ensuring that it met the project’s goals. The successful implementation of the RISC-V core lays a solid foundation for future work, including the addition of features such as control and status registers, support for multiplication and division operations, and the implementation of new instructions. Additionally, the modular nature of the design allows for potential future extensions, including debugging capabilities, further enhancing the processor’s versatility and usability in diverse scenarios.