Area and performance evaluation in the physical design of advanced integrated circuits

As integrated circuits scale to sub-5nm nodes, optimizing the power delivery network (PDN) becomes critical to balance area efficiency, routing resources, and power integrity. This study explores PDN architectural trade-offs in an advanced sub-5nm process, evaluating configurations such as stub-vs-stripe routing, grid pitch, and via-stack density. Using a standard-cell block (~1M gates), results demonstrate that stub-based PDNs enable superior area scaling (12% improvement over stripe-based designs) but introduce leakage and IR drop trade-offs. Newer technology nodes reduced leakage up to ~40%, underscoring process advancements. While aggressive scaling configurations achieved significant area savings, they incurred moderate IR drop penalties, whereas balanced designs maintained power integrity with only minor scaling compromises. The findings emphasize that PDN architecture choices can rival technode advancements in enabling area scaling, but holistic co-optimization of power, performance, and routing efficiency remains essential. This work provides a framework for PDN design in advanced nodes, prioritizing critical trade-offs to address scaling challenges.