Acceleration of Software Applications on FPGAs using High-Level Synthesis

We are living in a pivotal moment in history, witnessing a technological revolution unfold in real time, as the rise of AI rapidly reshapes the world around us. Due to increased data volumes, advanced algorithms, and improvements in computing power and storage, artificial intelligence and machine learning have soared in popularity today, causing extensive research to be dedicated to this field. A crucial component of these models are activation functions. These functions play a critical role in neural networks, as they enable AI/ML models to learn and represent complex patterns in data. However, due to their resource-intensive nature, more efficient solutions are needed. This brings forth the main purpose of this thesis, which was to develop more efficient implementations of the activation functions currently used in the industry and accelerate them on FPGAs. One of the various methods used for this design process is high-level synthesis design, which was also the methodology followed during this thesis, indicatively using Xilinx (AMD) tools, such as Vitis HLS and Vivado. The final product is a generalized LUT-based method of implementing activation functions, which can be used to accelerate many different functions, and can be easily integrated into neural networks. This method drastically reduces the amount of hardware resources needed to compute complex mathematical expressions, such as non-linear activation functions, achieving up to 97% reduction in LUTs and FFs as well as avoiding the usage of DSPs so they can be allocated to other resource-intensive blocks such as convolution layers, all while introducing accuracy losses of remarkably low values below 0.2%, in object detection networks. Using this solution, devices at the edge (such as IoT devices and smartphones) would be able to run more complex and advanced AI models, enhancing their performance.