Reti neurali spiking basate su CMOS e sinapsi: circuiti neuromorfici = CMOS-Based Spiking Neural Networks and Synapse: Neuromorphic Circuits

SNNs are one of the fastest-growing fields in neuromorphic computing and hold great potential for the next big revolution in energy efficiency, enabling both brain-like computing and real-time pattern recognition. Among these, the main challenges involve finding the best trade-off between power efficiency and area usage while preserving the accuracy and reliability of synaptic plasticity processes, such as Spike-Timing-Dependent Plasticity. The SNN architectures based on traditional CMOS technologies suffer from high power consumption and large areas; therefore, they are inappropriate to be deployed in a highly energy-constrained environment. Referring to these challenges, this work proposes an architecture of SNN on pure CMOS, designed and optimized using TSMC's 180 nm technology Cadence tool. Central to it is the establishment of a selection unit that acquires signals from pre- and post-synaptic neurons and subsequently generates eligibility signals that would help drive synaptic weight modulations. This methodology guarantees precise timing, which is crucial for effective learning and computational processes in neural networks. The architecture employs capacitance reduction strategies through the implementation of Medium-threshold transistors, which notably decrease power usage while attaining spatial efficiency within established performance benchmarks. The total power consumption significantly reduces from 35 pW to 3 pW. Additionally, the energy due to each spike is drastically reduced; from 2 pJ/spike to 3.57 fJ/spike. Another element of this architecture is the inclusion of error correction circuitry: the goal is to enhance reliability through the prevention of erroneous synaptic updates, especially with noisy or delayed post-neuron activations. This property makes the synaptic weights converge to fixed values for prolonged operational time and thus enhances the long-term reliability of the system. The present study focuses on energy efficiency, spatial minimization, and the dependability of synaptic plasticity to provide a holistic scalable approach for neuromorphic computing. This SNN system represents a very reliable low-power architecture suitable for resource-constrained environments and opens wide possibilities for future brain-inspired AI and any other applications to be developed in a low-energy and high-performance way. Therefore, the results of the STDP test compute energy consumption for pre-neuron as 38.77 fJ/spike and post-neuron as 22.82 fJ/spike.