Exploration and Modeling of Logic in Memory Architectures Thesis Abstract

Modern CPU architectures are based on the Von Neumann model, which consists of two components: the processing unit and the memory unit. While the processing unit has significantly improved over time, memory capacity has not kept pace, leading to a substantial performance gap between the two, known as the "Memory Wall." The Memory Wall has been a subject of discussion for years, with one proposed solution being the "Logic in Memory" (LiM) paradigm. This approach involves embedding computational units within the memory to reduce memory access, power consumption, and data-fetching latency. Additionally, LiM-based architectures enable parallel computation, as each memory bank has its own independent computational unit(s). To implement Logic in Memory architectures, emerging technologies such as resistive random-access memories (RRAMs), spin-transfer torque RAM (STT-RAMs), phase change memories (PCMs), and ferroelectric field-effect transistors (FeFETs) can be leveraged, as they offer advantageous features. Several LiM architectures have been developed using these technologies, with varying designs in terms of bank structure and overall architecture, though they share common principles. However, there is currently no high-level description of these designs, making it difficult to explore system integration or apply benchmarks. Therefore, it is crucial to develop an Architectural Model of Logic in Memory that can serve as a standard and is compatible with common interfaces like the Open Bus Interface (OBI). The objective is to create a high-level architectural model that fully integrates the LiM paradigm, incorporating key features from existing implementations while addressing technology choices, algorithms, main architectural blocks, data processing, and mathematical operations performed. To achieve this, a custom assembly language was developed, inspired by the RISCV instruction set for its proven effectiveness. This custom language borrows from the RISCV structure while providing specialized functionality. Instructions are stored in an instruction memory that initializes at startup and supplies the instruction decoding unit during computation. The architecture operates in parallel, with each bank containing its own Arithmetic Logic Unit (ALU), register files, and memory array, all interconnected via a bus for seamless communication. The model operates in two modes: Memory mode (executing LOAD and STORE operations) and LiM mode (performing bitwise and mathematical operations). The model was tested within the X-Heep microcontroller, and algorithms were executed to compare performance between CPU-based execution and accelerator-based execution. The benchmarks demonstrated that the LiM was up to 10 times faster than the CPU, depending on the specific benchmark used. Finally, the architecture was synthesized using the SAED14nm library and predefined SRAM cells. However, to optimize the design, a custom library for the accelerator is necessary.