ADC Testing: Comparison between new test methodologies and standard ones

This thesis work explores new methodologies to be implemented with the aim of minimizing the time required to test the nonlinearity components in Analog-to-Digital Converters (ADCs), namely the Differential Nonlinearity (DNL) and the Integral Nonlinearity (INL). Traditional approaches to perform these measurements are the Ramp Histogram Test (RHT) and Sine Histogram Test (SHT) techniques. However, these methodologies are very time-consuming, especially when applied to high-resolution ADCs, as they require a significant number of samples to be acquired and consequently a considerable acquisition time. To address this limitation, this thesis work aims to investigate two possible algorithms for DNL and INL error evaluation by drastically reducing the number of samples required and even improving the accuracy of the measurements. The two proposed algorithms, one developed by Yu & Chen and the second one developed by Aswin, employ two different approaches to evaluate the linearity of the ADC. The Yu & Chen algorithm uses a segmented non-parametric model to estimate the DNL and INL with a reduced number of samples, thus decreasing the acquisition time during the test. The Aswin approach, instead, makes use of a linear component and a non-linear component to represent the INL, exploiting ADC major code transitions and cosine fitting to construct these components, obtaining a more robust representation of the errors by minimizing the number of acquisitions. The work includes the implementation of these algorithms, initially through their simulation via MATLAB and subsequently the conversion of these into C++ code with the purpose of programming the SPEA DOT800 tester, used to test different electronic devices, including ADCs. The test was conducted on the AD7609 converter, an 18-bit ADC. Some test parameters were modified, including the sampling frequency, number of acquisitions, frequency of the input signal to the converter, and its amplitude. This was done to identify the optimal configuration for maximizing the test result and to verify the repeatability of the two algorithms. A comparison of the obtained results demonstrates that both new methods offer superior performances than traditional methodologies and reduce the test time by more than 95%.