Test and Reliability Enhancement on a RISC-V SoC architecture

System-on-Chip (SoC) technologies are crucial in electronics-driven fields, integrating processors, memory, and peripherals into single-chip solutions. These systems offer substantial improvements in performance, energy efficiency, and costs but introduce increasing demands for reliability and security as they grow in complexity. In light of these challenges, Design for Testability (DfT) methodologies are vital, supporting robust testing, diagnosis, and fault isolation. Key DfT features such as Built-In Self-Test (BIST), standardized test access protocols, and fault-tolerant mechanisms enable the development of reliable, high-quality SoCs. This work focuses on the RISC-V Instruction Set Architecture (ISA), which provides an open-source, flexible framework ideal for diverse applications. The CVA6 core by OpenHW was selected for its scalability and adaptability within a DfT-equipped SoC architecture. The SoC design integrates memory subsystems, external memory interfaces, and essential peripherals, all structured to ensure both functionality and reliability and an advanced DfT architecture. Testing and verification were conducted through simulation, synthesis checks, and formal verification, with emphasis on analyzing power, area, and timing to optimize performance metrics across multiple operating conditions. A crucial component of this project was the implementation of monitoring tools, which enable real-time observation of the SoC’s operational state, including the critical CVA6 core. Different types of monitors can be selected and added, allowing flexible configuration to track specific operations and enhancing fault detection and system resilience during testing. These monitors can be grouped, with a unique signature generated for each group, which is then utilized by VC ZOIX during fault simulation to increase coverage, particularly since the monitors are inserted in low-observable points of the design. Each monitor can be enabled, cleared, or reset by writing the appropriate value to its corresponding Control and Status Register, with a dedicated register reserved for each unique output signature. This structured observability aids in ensuring system integrity under realistic operating scenarios. The results confirm that integrating DfT into an SoC with a RISC-V-based CVA6 core meets performance requirements while ensuring robust fault management capabilities. By establishing a modular testing environment, this project lays the groundwork for future SoC designs that prioritize both security and reliability, demonstrating the effectiveness of an open-source, test-focused approach in advanced semiconductor development.