polito.it
Politecnico di Torino (logo)

Design of a high-speed voltage comparator for a GaN HEMT active gate driver

Iride Blu Serio

Design of a high-speed voltage comparator for a GaN HEMT active gate driver.

Rel. Franco Fiori. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2024

[img]
Preview
PDF (Tesi_di_laurea) - Tesi
Licenza: Creative Commons Attribution Non-commercial No Derivatives.

Download (5MB) | Preview
Abstract:

GaN HEMTs have been gaining popularity in power electronics applications due to their advantages with respect to silicon power transistors, such as higher speed, lower ON resistance, larger breakdown voltage and smaller size. Driving this new generation of power transistors, however, presents some challenges: the large slew rates (for both voltage and current) associated with high-speed operation can lead to EMI and voltage oscillations. When it comes to gate voltage range, GaN HEMTs have stricter requirements compared to silicon power transistors, which means that these voltage oscillations can either inadvertently turn-on the device or outright damage it. This thesis focuses on how to detect voltage oscillations after the turn-off of the GaN device through the use of a CMOS comparator built into the active gate driver. The most critical parameters when designing this comparator were its speed and the trade-off with power consumption. Several existing topologies were analysed to check whether they could match the provided design specifications, until a suitable one was found. The final schematic involves a self-biased differential amplifier, an inverter and a monostable circuit, plus an ESD protection and conditioning circuit at the input. The document presents the design steps as well as the results of the simulations. The inputs to the comparator are a constant reference voltage (generated through a bandgap circuit and equal to 1.242 V) and the voltage ringing at the gate of the GaN HEMT, which is modelled as a triangular impulse of duration 1 ns, period equal to 10 μs and amplitude variable between 1 and 10 V. The voltage supply is set at 3 V. The output is loaded with a 100 fF ideal capacitance to simulate a buffer, whose design is beyond the scope of this thesis. The comparator’s rail-to-rail output switches successfully in compliance with the provided specifications in terms of voltage, power consumption, and operating temperature. The monostable circuit keeps the output stable for about 10 ns after the impulse is detected, so that the active gate driver’s control unit can interpret the transition correctly and protect the GaN device. In conclusion, this high-speed comparator with wide input range can be considered a useful tool to monitor the voltage oscillations at the power device’s gate terminal, providing a safety feature for the active gate driver which may help increase reliability and lifespan of the GaN power device.

Relatori: Franco Fiori
Anno accademico: 2024/25
Tipo di pubblicazione: Elettronica
Numero di pagine: 73
Soggetti:
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: Nuovo ordinamento > Laurea magistrale > LM-29 - INGEGNERIA ELETTRONICA
Aziende collaboratrici: NON SPECIFICATO
URI: http://webthesis.biblio.polito.it/id/eprint/33243
Modifica (riservato agli operatori) Modifica (riservato agli operatori)