Delta encoding of failure bitmaps for efficient compaction and on-chip retention of diagnostic data collected on embedded RRAM memories

Embedded System-On-Chip memory capacity and reliability required by the Automotive industry is constantly growing. For this reason, manufacturing companies are moving to create faster and cheaper memories to supply the high demand for chips by Automotive companies. Since the correct working of these memories is crucial for such a delicate environment as the automotive, these memories must be deeply tested to be completely functional without any error. Infineon Technologies Inc. is developing an innovative technology for embedded memories called Resistive Random Access Memory – RRAM. This kind of memory is faster and cheaper than classical FLASH technology but is also subject to errors due to its chemical structure. To ensure that the System-on-Chips (SoC) sold to the companies are free from these errors, these memories are thoroughly tested before reaching the market. The fastest way to test the memories is to have an on-chip test so that both the algorithm and the results are computed and saved on the same Device under Test (DuT). These devices have a small, dedicated, on-chip memory space to store diagnostic data. When this storage space is saturated, it must be downloaded to the tester, which is a very long operation. Being efficient allows both to do fewer downloads and to download more data simultaneously. It is also important to note that at each test step, the tester is able to analyze multiple devices concurrently. The slower devices (the ones that have more faults and require more buffer dumps) are the bottlenecks of the test, as the tester needs to wait for them to complete their verify before continuing to the following test step. A single SoC can be tested multiple times with different kinds of tests, and saving each time the test result inside the same chip could be unfeasible, again due to the small capacity of the chip. The simplest way to test the bits of a memory is to map each of them as a list of coordinates, but this can produce a massive amount of data that, in most cases, will not fit in the short storage capacity of the SoC. For this reason, Infineon adopted an efficient and lossless compaction algorithm that represents the faults in the memory through a shape encoding technique. The goal of the thesis is to make this shape encoding algorithm even more efficient by, instead of storing all the results of the tests, saving just the differences among multiple test steps. For example, a bit that is a stuck-at fault at a given test step is likely to fail again in the following steps, and in this case, it is redundant to encode the same diagnostic information. In a mechanism unique to RRAM, the stuck-at-fault condition can be temporary, so it is helpful to know when the bit becomes functional again. To achieve maximum encoding efficiency, the algorithm maps the faults at the first test, collects the differences from the following tests, and encodes them following the compaction rules. Using this method and efficient compaction algorithms, it is possible to reduce the diagnostic space used on the dedicated on-chip memory by up to 60%.