High-Throughput LDPC Multi-Decoder Exploration with novel Quantization and Reconstruction Method

The 3GP consortium envisions breakthrough changes in technology of the next decade. Among them, tactile internet, holograms, autonomous vehicles and telemedicine. However, the key enabling milestone, an Ultra Reliable Low Latency Communication channel, must be achieved. Among the needed technological innovations, decoders play a pivotal role in the stack of the RF systems. LDPC decoders have become the go-to choice thanks to their rapid convergence. Very high-throughput unrolled LDPC decoder have been implemented but find no practical application due to high area requirements and networking congestion issues. To alleviate the routing congestion issues, the effective RCQ paradigm was proposed. We leverage the RCQ paradigm and aggressively quantize nodes' messages to implement an area effective FPGA-ready high-throughput hierarchical multi-decoder system. The proposed architecture is flexible and can handle in an efficient way multiple frames in parallel, even with different Signal-to-Noise Ratios (SNR). This is effective for modern Multi-User scenario. The architecture can support all LDPC codes. Simulations with 802.11 IEEE code with N=648 and R=5/6 yield throughput of up to 568 Mbps. FPGA implementation reports 21.5 % saved area, considering both logic elements and memories, thanks to the aggressive quantization being employed.