Matrix Acceleration on Processor Using State-of-the-Art Technology Corners

The rapid advancement in machine learning has sparked a need for application specific hardware to handle diverse workloads, from server-grade training to edge-device inference. This work focuses on designing a Precision-Scalable Multiply-Accumulate unit for matrix multiplication accelerators, which is optimized for a state-of-the-art technology node. The analysis evaluates the impact of temperature robustness on Performance-Power-Area metrics, highlighting the trade-offs in design choices for the Modified Booth Encoding, the Carry Save Adder accumulation and the Parallel Prefix addition. The results show that optimizing for a specific temperature corner can reduce dynamic power by 3-4% while keeping the remaining metrics constant.