UVM testbench development for I2S protocol verification

Modern digital integrated circuits are increasingly becoming more and more complex, with several internal logic blocks, submodules and interconnections. Not only the functionalities they implement are quite complicated, but they must perform their tasks with stringent timing, area and power requirements. Due to these reasons, verification of integrated circuits is becoming more important. Thanks to the verification process, it is possible to make sure that new devices behave according to their specifications in a timely manner, reducing the time to market. Moreover, it allows to significantly shrink the number of bugs reaching the physical production stage of chips, preventing costly manufacturing errors and increasing the product reliability. The introduction of the Universal Verification Method (UVM) has drastically changed the way verification is carried out, introducing a standardized, robust, modular and flexible environment, enhancing the interoperability and facilitating the exchange of code between different teams and projects. This thesis aims at verifying an I2S protocol master unit developed by TDK Invensense, using the SystemVerilog language and the UVM framework. After a preliminary study on UVM and SystemVerilog language through Cadence courses, the obtained notions have been applied to develop a full UVM environment with classes and tests, written to cover one, or more, specific features of the Device Under Test (DUT), needed to fully verify the DUT. The results obtained by applying the aforementioned tests have been thoroughly analyzed and evaluated. Neat and intuitive coverage reports have been generated through the use of regression testing and merging in combination with SystemVerilog and UVM coverage features. The generated reports showed a quite complete verification of all specifications written in the Test Plan. The remaining not covered points have been investigated to understand whether they represent not reachable scenarios or tests related bugs. For the few reachable not covered points, some ad hoc tests have been created by driving specific signals to recreate the correct stimulus generation, while the others were removed through refinement steps adding justification on why could not be covered. Thanks to the combination of the random stimuli generation and the constrained one, a full coverage of the master unit has been reached.