UVM-based functional verification of a high-performance memory controller IP with outstanding capability

As the complexity of modern Integrated Circuits (ICs) grows, ensuring that these designs function as intended becomes increasingly challenging. Verification plays a crucial role in this process by detecting bugs early, when they are significantly less costly to fix. Traditional verification methodologies, such as manual simulations, have struggled to keep pace with the growing complexity of ICs, particularly in functional verification. To address these challenges, the Universal Verification Methodology (UVM) has emerged as a standardized framework, enabling scalable, modular, and reusable verification environments, thus overcoming many of the limitations of older approaches. This thesis presents the functional verification of a high-performance memory controller, a key component embedded in a hardware accelerator IP. The Design Under Test (DUT) is highly configurable, capable of managing multiple concurrent access requests to static random-access memory (SRAM), organized in banks, through various ports, each following specific protocols with unique priorities. The complexity of the design necessitates a robust testbench capable of efficiently handling different protocols and managing multiple interfaces. In response to this, a UVM-based testbench was developed, which is highly generic and configurable, reflecting the flexibility of the memory controller’s design. The testbench adapts to various configurations, including the number of ports and protocols, ensuring seamless verification across different design instances. Moreover, the verification environment is designed to validate the memory controller’s functionality, manage request handling, and ensure adherence to timing and priority constraints, simulating various scenarios to ensure correctness under all operating conditions. The verification environment leverages coverage-driven verification techniques, utilizing assertions, covergroups, and coverpoints to ensure thorough testing of the controller’s functionality, focusing on port independence, bank selection, request prioritization, and out-of-order execution. Comprehensive simulations were conducted, resulting in 100% functional coverage and 100% code coverage, demonstrating the effectiveness of the developed testbench. This work underscores the importance of UVM in the verification of complex hardware designs and highlights the capability of a well-constructed testbench in meeting the growing demands of modern IC verification.