Automatic detection of timing-violating, non-automatically-fixable paths

A problem that engineers often face at the end of the physical design flow consists in some paths in their design violating the given timing constraints. EDA tools whose purpose is fixing these violations do exist and are frequently employed, but they are not able to significantly speed up paths with specific properties: in these cases manual intervention by the engineers is needed. These paths that cannot be automatically fixed by the aforementioned tools, which will be referred to as Non-Automatically-Fixable Paths (NAFiPs for short), are characterised by the fact that they contain poorly routed nets or high-delay memories (like RAMs) and need very targeted fixes. Commercial tools cannot identify NAFiPs or automatically fix what’s causing them, requiring engineers to manually examine numerous paths. They must also examine delays, transition times, and net shapes to determine the fixes needed to achieve the required performance. This thesis, developed as an internship assignment inside Qualcomm Technologies Incorporated (Cork site), aims to design and implement a system that detects potential NAFiPs that violate setup time constraints automatically, tolerating some false positives to make sure that all the problematic paths are detected. It simplifies the task of identifying non-automatically-fixable paths, devising and applying the appropriate interventions.