Fault grading at analog-digital boundary in mixed signal systems on chip

With the rapid development of consumer electronics, Internet of Things, smart cars and other fields, more and more application-specific integrated circuits (ASIC) need to be developed and projected. In particular the analog mixed signals (AMS) ASIC can interface themselves with analogic modules and they can be applied for different purposes. An AMS ASIC can be summarized as it is constituted by a digital logic part that elaborates and processes the signals from the analogic modules. The continuous increase in circuit complexity of AMS ASIC also brings challenges to circuit testing. During their fabrication, some physical defects between the interconnections of the analogic modules and the digital section could arise. The focus of this thesis is the development of a testing flow for the analog-to-digital (A/D) interface in AMS circuits able to find these defects. To do so, we first refer to a fault model, in particular the stuck-at fault (SAF). We suppose that every interconnection line can be stuck to a precise value i.e. 0 or 1. Then we developed a fault injection mechanism including circuit models ( systemverilog for the analogic parts) and fault injection script that injects a stuck-at 0 or stuck-at 1 on the A/D connections. To test the different faults we used functional test patterns i.e. patterns that are applied on the input and the output signals of the AMS ASIC. In particular, we start from already existing functional tests for the analog modules and check their coverage on A/D connections. These functional stimuli were testbenches that perform read/write through A/D interfaces. We also improve the test stimuli to detect as many defects on the A-D interfaces. Overall, we start with a tool able to simulate test stimuli on the AMS ASIC A/D interconnections and then we use our script to inject the faults and compute the fault coverage. Finally, we have done some analysis on the fault coverage to identify untestable faults and consider a possible improvement for the test stimuli to achieve test coverage. Testing the A/D interconnections have also another positive effect on the AMS ASIC. By changing the values on the A/D signals, we also apply some stimuli to the digital section of the ASIC. This last part is tested by referring to structural testing, for example scan testing. This thesis also focuses on applying this functional test pattern to digital logic and see if produces some improvement on the fault coverage. In particular we start from the fault coverage obtained after the simulation of the scan test patterns, we used a fault simulator to apply the functional stimuli on the remaining untested faults and we checked if an improvement was produced. In summary, this thesis develops a flow for the detection of defects on A/D boundary signals in AMS ASIC by starting from existing test stimuli and also improving these last ones to achieve better coverage. This new testing check is important for the quality and reliability of AMS ASIC. Furthermore, it also checks if the functional test stimuli of the interconnection are able to improve the digital section fault coverage.