Core Testbench Boot Sequence Optimization

My master thesis project focuses on optimizing the boot sequence execution time in the CPU Core Testbench environment. The primary goal is to reduce the time spent executing boot instructions individually on the RTL by directly forcing the system register values at boot, extracted from the model, onto the RTL. The project is divided into three key phases: In the first phase, the objective is to extract paths to all system registers within the CPU core's various modules. This involves Python coding within the main code of the design tool used to automatically generate the system registers. The second phase focuses on mapping system register names to their corresponding boot values, obtained from the model, during the boot sequence. This requires modifying the C++ code of the tool responsible for instruction generation and execution on the RTL part of the Testbench. The final phase involves coding in SystemVerilog to integrate a new component into the Core Testbench that will force the boot values onto the RTL, using the map and paths generated in the previous phases. This enhancement is expected to significantly reduce the time required for CPU Core verification tests.