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Mina Samadian
Restructuring Real-Time Hardware-in-the-Loop (RT HIL) Models Using a Multicore Approach: Enhancing Component Reusability and Intellectual Property Protection.
Rel. Luciano Lavagno. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2024
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Abstract: |
This thesis aims to restructure a real-time model for a hardware-in-the-loop (RT HIL) system incorporating an inverter, electric motor, mechanical model, and bus simulation. Hardware-in-the-loop simulation is used to develop and test complex, real-time embedded systems. It allows for integrating physical and simulated components to create a comprehensive testing environment, enabling developers to evaluate the performance and behavior of control systems under real-world conditions without the need for a complete physical prototype. This method is precious in the automotive industry for safely and efficiently testing and validating electric motor control systems and other electronic control units (ECUs). The restructuring utilizes a multi-core approach to enhance the reusability of individual components while preserving intellectual property. The resulting model is composed of two synchronized cores: the first core is a white box, providing full access to the code for complete calibration capabilities, the addition of new parts, and comprehensive bus simulation modeling. The second core is a black box containing all intellectual property using only the build results. This setup allows future development to use only the black-box core build while enabling full access to new parts development exclusively on the white-box core. The multi-core architecture ensures correct data propagation between the processor's cores and FPGA, optimizing performance for complex simulations. The RT HIL system includes a controller developed on Simulink that runs on the HIL's real-time processor and is used for open-loop testing. The restructured model was validated using the open-loop integrated controller. The second step involved validation with the real device under test, composed of an actual control board (without power stage) for a high-speed PMSM motor connected by wire to the HIL. The system demonstrated robustness and high accuracy in motor simulations, maintaining performance in real-time scenarios and closing the loop. This new modular architecture allows for the proper compromise of calibration, new development, and intellectual property policy compliance. |
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Relatori: | Luciano Lavagno |
Anno accademico: | 2023/24 |
Tipo di pubblicazione: | Elettronica |
Numero di pagine: | 75 |
Soggetti: | |
Corso di laurea: | Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering) |
Classe di laurea: | Nuovo ordinamento > Laurea magistrale > LM-29 - INGEGNERIA ELETTRONICA |
Aziende collaboratrici: | Kineton Srl |
URI: | http://webthesis.biblio.polito.it/id/eprint/31933 |
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