Process Simulation and Compact Modeling for a NS-GAAFET

In the most recent years, semiconductor-based devices and technologies have experienced fast improvements, resulting in important advancements. To enhance their performances, semiconductor devices have been scaled in geometrical dimensions and voltages, following Gordon Moore's laws. However, scaling has led to the emergence of detrimental effects, such as short-channel effects and substrate leakage currents (respectively summarized in the DIBL and SS parameters) forcing designers to seek novel devices and technologies with improved electrostatic control and reasonable drive current and speed. In recent times, an important transition occurred with the introduction of 3D devices such as FinFETs. However, FinFETs have also become inadequate for the technological nodes of today due to some limitations. In this framework, stacked NanoSheet (NS) GAAFETs (Gate-All-Around Field-Effect Transistors) have been considered the most promising candidates for the replacement of FinFETs for sub-7-nm technological nodes. The aim of this work is, starting from the experimental process, to obtain a matching between the aspects of the NS-GAAFET that have been analyzed. A compact model that is more closely related to the actual physical behavior of the device is missing. Firstly, a comparison has been carried out between a numerical simulation of the technological process of the NS-GAAFET device and an experimental one. Process simulations have been compared with experimental data to highlight the main differences between the numerical simulations and the actual technological process, in particular regarding the process steps peculiar to the NS-GAAFET device itself. Electrical simulations have been, then, carried out to investigate the DC characteristics of the fabricated devices. In the second part, a matching of the physics-based model with the BSIM-CMG-NS compact model has been done. Modifications in the Verilog-A code of the BSIM-CMG-NS were introduced to make the compact model match the physics-based simulator results. In the last part, AC simulations have been done at the device level to investigate the impact of inner and main spacers in the time-varying regime. The choice of a low-k dielectric as the main and inner spacer turns out to be important for NS-GAAFET small-signal AC behavior, due to a reduced capacitance, which is peculiar to the NS-GAAFET device itself. Similar results have been obtained in circuit-level simulations, where the oscillation frequency of a Ring Oscillator of 5 ports has been retrieved for different main and inner spacer materials.