5G protocol stack simulation acceleration via FPGA

Currently, the increasing demand for computation speed requires advanced technology to generate the results at a relatively high performance. In this case, the FPGA platforms could be one possible choice due to their possibility to accelerate computation based on the highly optimized critical part at the hardware level, its parallelism, and low latency, which can be more efficient compared with general-purpose CPUs. By exploiting High-Level Synthesis (HLS), FPGA platforms can deliver an optimized hardware implementation with relatively low design effort. HLS accepts as input high-level programming languages for example C++, and by exploiting user-written pragmas and configuration directives, it can automatically generate the hardware implementation with various optimized architectures. The 5G protocol stack simulation acceleration developed in this thesis exploits the Xilinx Alveo U280 Data Center Accelerator Card as the FPGA platform for improving computation speed throughout the whole downlink and uplink stack. The accelerated stack contains 5 modules: Orthogonal Frequency-Division Multiplexing (OFDM) modulator, over-sample filter, fifth-generation new radio (5G-NR) channel model, down-sample filter, and OFDM demodulator. The OFDM modulator and OFDM demodulator use the Xilinx LogiCORE IP Fast Fourier Transform (FFT) core, used for pre and post-processing data from the Transmitter and the Receiver. The over-sample filter and the down-sample filter are mainly used for up-sampling, down-sampling, and filtering the data sent to the 5G-NR channel model in order to have a better performance. These modules utilize finite impulse response (FIR) filters, with different numbers of coefficients. Even though the transmitter and receiver have a different number of antennas, it only affects the input and output matrix sizes, while the hardware resource utilization for the filters depends only on the FIR filter architecture and the required performance. The channel model represents a multiple-input and multiple-output 5G-NR communication channel. In order to have the best performance on the FPGA, A streaming communication should be implemented between the modules. In this case, the throughput of different modules must be balanced, hence some modules need to increase their sampling frequency by using an optimized algorithm or using bursts when reading data from the global memory, while some modules ought to decrease their sampling frequency to reduce the utilization of the hardware resources, so that the final hardware can be accelerated in its entirety on an FPGA. This project aims at combining all the previous 5 modules and generating an integrated physical hardware implementation on Xilinx Alveo U280. The whole process including software emulation, hardware emulation, and the final step, which generates a bitstream for the hardware, follows the Xilinx Vitis hardware accelerator design flow.