Design of RISC-V Based Dual-Core Processing Unit for Sensor Application

Smart sensors are electronic systems that embed a sensor and the digital logic to process the captured data in a single integrated circuit. Many applications involving these systems have real-time requirements, imposing a restriction on the time window in which each sample must be captured and processed. However, the required processing is often too computationally heavy to handle, within the time budget, using an area and power-constrained embedded CPU. One solution to this problem consists in offloading expensive operations to dedicated hardware (HW) accelerators, which can execute a (set of) specific processing tasks faster and more efficiently than a CPU. An example is digital signal processors (DSPs). The purpose of these processors is to handle in an efficient way standard operations done one signals coming from a monitored environment like filtering. DSPs are a cost-effective solution to increase the overall computational power of a smart sensor. Common operations like finite impulse response (FIR) filter and Fast Fourier Transform (FFT) have a regular structure which makes them well-suited for a HW implementation. In an architecture that includes a CPU and HW accelerators, new aspects to consider come up, like the communication between the modules. The design space to explore is vast, and concerns both the complete system, as well as the internals of each module, the memory hierarchy, and so on. The goal of this thesis is the study and the implementation of a heterogeneous CPU plus accelerator solution focused on smart sensor applications. The objective is to maximize performance, while keeping the area and power consumption to a minimum and maintaining a good degree of flexibility. In fact, the system is designed so that both the CPU and the accelerator can be replaced without compromising their communication and the overall behaviour of the system. The Main CPU is a minimal RISC-V processor implementing the RV32I instruction set architecture (ISA), with a very small footprint. For this thesis, some additional features were implemented such as a Nested Vector Interrupt Controller (NVIC) as well as an AHB bus interface for the main core. The accelerator is an extremely optimized pico-processor. It implements a custom ISA to provide highly optimized instructions to support DSP applications. The instruction memory is formed of many RTL ROM, one for each algorithm, guaranteeing a optimal area occupation while also reducing the power consumption. The two processing elements are connected by a 2x2 AHB bus matrix where the two masters are the RV-core and the sensor, while the slaves are the accelerator and the memory of the RV-core. Even though there are better solutions for power and area, AHB was chosen due to its flexibility and scalability. The result is a dual-core system where the main core acts as a scheduler and can be configured to receive data from a sensor and use this data in an accelerated operation, delegated to the second core without blocking the main one. The activation and execution of the accelerator is done by calling functions provided in a C library which will set the appropriate registers for the accelerator execution. The conclusion of each phase (data from sensor available and completion of the accelerator) is notified through interrupts. The implemented system provides a 73% improvement in the time necessary to perform an 11 taps FIR filter, while occupying only 40% more area with respect to a version without HW accelerator.