Integrated circuit Back-End of line analysis and modeling for future node pathfinding

The decades-long strategy of transistor downscaling for miniaturization and improved power-performance-area (PPA) is facing limitations beyond front-end of line (FEOL) elements. Shrinking back-end of line (BEOL) interconnects leads to resistance (R) and capacitance (C) issues, causing delays that hamper design performance. Understanding routing and its correlations to design criteria is crucial. PnR results hold data on path details, but extraction flows are needed to access this. Extracting data is vital for analyzing and optimizing chip designs to tackle contemporary technological challenges. The aim of this project is to improve, extend, and increase the features of the existing extraction flow which captures and connects the exact topology of paths from a signoff database to other circuit features and physical parameters of a given chip design, node, and technology. Crucial criteria used by the EDA tool to achieve routing optimizations within timing and area constraints are deduced from a statistical analysis. Additionally, a novel mapping method is proposed to integrate electrical and statistical analysis into an enhanced ring oscillator (eRO) which aims to be more accurate for benchmarking than the usual ring oscillator (RO). This eRO model turns out to be essential to accurately predict the impact of new BEOL booster technologies or BEOL stack optimizations. A comprehensive assessment of the impact of the BEOL on cell delays provides insights into the complete contributions of resistance and capacitance components within the circuit. This evaluation facilitates the determination of overall signal path delays, leading to the calculation of a predicted circuit’s frequency of operation as a function of modified or scaled circuit parameters.