Assessing the Effectiveness of Software-Based Self-Test Programs for Static Cell-Aware Testing

Testing and verification of integrated circuits (ICs) is a vital process to ensure they meet performance standards. IC manufacturing can introduce various physical irregularities, including transistor issues and short circuit connections, leading to operational misbehaviors. Test generation aims to find stimuli that uncover these defects while applied to the inputs of the IC, and fault models provide a framework for the process. Various fault models have been implemented over the years which try to simulate different possible defects in the structure of IC. Stuck-at and Transition delay fault models are the two traditional fault models widely used. Other models such as Path delay faults and Cell-aware faults have been defined and utilized which take into consideration the defects possible in a lower level. These models have become more vital with the ever-shrinking size of transistors and ICs with advancement of technology. The focus of this thesis is on generation of test patterns which can maximally detect the defects present in the IC in a functional environment. Functional testing is a concept of testing an IC as a black box thus considering the primary inputs and the primary outputs of the circuit as the only access points to the IC. Functional test patterns are patterns responsible for exciting faults which can be observed in the primary outputs of the IC and produce results which are faulty compared to the healthy circuit. Test programs are generated for the purpose of generating test patterns to detect the faults in the IC. The main objective of thesis is to use already existing test programs and enhance them using other test programs which are called Enhancer Test Programs in this thesis. The flow begins with the extraction of test patterns, utilizing SBST (Software-Based Self-Test) based test programs to obtain patterns for subsequent simulations. Following this, the fault list is created using a previously established flow, integrating Python and the Z01X tool for fault simulation, with further refinement to include only module-specific faults. The next step involves fault simulation, employing the Z01X tool to execute simulations using test patterns generated by both the main and enhancer test programs. Specific fault list generation is then implied, facilitated by custom software developed throughout the thesis, resulting in a new fault list encompassing faults covered exclusively by the enhancer program. The process proceeds to a test program optimization loop, exclusively utilizing the enhancer program as a test pattern generator. This stage employs the Test program optimizer software which is another software developed in the thesis to eliminate obsolete patterns from the test program which do not contribute to the detection of any fault existing in the fault list. Finally, the flow concludes with the generation of a new and enhanced test program, incorporating the remaining instructions from the optimization process into the main test program. In conclusion, this thesis contributes to the detection of defects in ICs that are not commonly excited with the existing test programs and as a result, signifies a profound impact on the quality and reliability of integrated circuits, as it approaches the coveted goal of near-perfect coverage.