Definition of a verification flow for High-Level Synthesis IPs: Case study on functional coverage applied to High Level Synthesis blocks in a C++ and Universal Methodology environment
Stefano Moncalvo
Definition of a verification flow for High-Level Synthesis IPs: Case study on functional coverage applied to High Level Synthesis blocks in a C++ and Universal Methodology environment.
Rel. Maurizio Martina, Guido Masera. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2023
Abstract
High-Level Synthesis (HLS) tools are becoming increasingly important in simplifying the design process for digital circuits due to the growing complexity of digital design. These tools enable designers to use high-level programming languages to develop Register Transfer Level (RTL) circuits, thereby reducing design complexity and time-to-market. With HLS, designers can develop algorithms and use the tool to explore various hardware implementations, such as adjusting the number of pipeline stages, loop unrolling, and meeting area and latency constraints. However, the use of HLS requires the establishment of verification flows for both high-level design and RTL generated by the tool. This thesis, conducted at STMicroelectronics, builds on the work of Jiangxi Wu and Giacomo Spinello, who developed the verification plan for the high-level Design Under Test (DUT).
The aim is to complete the verification plan by introducing functional coverage into a tool-generated Universal Verification Methodology Framework (UVMF) and the high-level testbench
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