On approaches to assess the effectiveness of Software Implemented Hardware Fault Tolerance (SIHFT) mechanisms for automotive application

In recent times, automotive systems, and in general all the safety-critical fields, are increasingly entrusting micro-controllers to perform complex and delicate tasks, also concerning safety-related functions. This extensive use of processors has consequently led to the need to make them more reliable and robust against errors that may lead to the violation of a safety goal, avoiding any unreasonable risk. For what concerns the systematic errors, they can be addressed and avoided at the design stage, paying particular attention to the item testing. On the other hand, Random Hardware Failures (RHFs) cannot be avoided nor predicted deterministically. The main causes behind Random Hardware Failures can be attributed to corrosion, thermal stressing, wear- out, radiations, and manufacturing defects. The consequences of a Random Hardware Failure can be a bit flip or a stuck-at-bit in any element (memory, buses, interconnect, logic/arithmetical components) of the system-on-chip, leading to the malfunctioning of the critical software, with performance degradations or safety hazards. To cope with this type of failure, the methodologies that were deemed most suitable were Software-Implemented Hardware Fault Tolerance (SIHFT) techniques, exploiting the software to detect hardware failures. The reasons that led to this choice are the undoubted advantages, namely the reduced costs, and higher flexibility and scalability. This thesis has the goal of evaluating the effectiveness, in terms of Diagnostic Coverage and in compliance with the automotive functional safety standard ISO26262:2018, of two proposed and implemented Software-Implemented Hardware Fault Tolerance techniques in a processor-in-the-loop scenario. Two different SIHFT techniques have been implemented for hardening the designed benchmark applications: • Hybrid Data Hardening (HDH): in order to cope with faults affecting the data values. This approach relies on the key concepts of data diversity and instruction duplication. • Control Flow Checking (CFC): this technique addresses the so-called Con- trol Flow Errors, detecting any illegal path in the execution flow. The proposed method demonstrated itself a promising approach for hardening critical software against Random Hardware Failures. By analyzing the results obtained from various Fault Injection campaigns performed on both ISA-level emulators (RISC-V) and on real hardware (Infineon TriCore), it was exhibited the detection capabilities of an average 16% of RHFs considering HDH and up to 45% of RHFs considering CFC. Due to the lightweight these techniques can be easily implemented in existing software and integrated with other detection mechanisms present in the system.