Generalized UVM testbench framework for verification of eFPGA devices

This thesis presents the work done in six months at Menta S.A.S., a company based in Sophia Antipolis, France. The final product of this work is a verification environment controlled by command line, fast to learn and easily extendable. This environment relies on a run of Origami Programmer (TM), a proprietary software by Menta, to generate the necessary files for the simulation of their architectures, followed by a validation in a System Verilog testbench. The System Verilog testbench uses Universal Verification Methodology libraries and is automatically modified by several Python and bash scripts depending on the information output by Origami Programmer to match any eFPGA architecture. Since operating an eFPGA means to configure it to implement a specific application, then the automatical setup of the testbench has to take the selected application into account. This new verification environment will be called UVM Flow and will be fully generic with respect to Menta architectures and customer's applications.