Implementation of UVM-Based Framework for Enhancement of DFT DV Flows

One of the main issues that companies have to face is the presence of legacy systems: tools, methodologies, and processes that are not updated over time and that can become a relevant bottleneck in company production. The issue of legacy systems is present in the context of Apple’s Design-For-Test team. Specifically, during the Design Verification (DV) phase, where the design of a chip is verified through software simulations, the engineers have to manually check that the behavior of some specific signals is the one expected. This step is time-consuming, repetitive, and error-prone. In this Master Thesis, the process of developing an automation tool able to verify the behavior of a chip's signals during the Design Verification is presented. The tool consists of a library of checkers (i.e., SystemVerilog code able to verify a specific behavior of the signals) which are instantiated inside the test bench used to run the DV simulations using a UVM module. In this way, the instantiated checkers behave as a probe, reading in real-time the values assumed by the signals and internally verifying that their behavior is the expected one. At the end of the simulation, the engineer is informed of the outcome of each checker, possibly including messages to provide insights on the causes of an error. The benefits provided by the tool lead to its extension to solve a different limitation of Apple’s flow. Specifically, when the playback simulations are executed, the analog signals are not present. As a consequence, the engineers cannot perform any waveform review and a comparison with the software simulation of the chip’s design is not possible. For these reasons, an improvement of the tool is performed, by allowing the presence of analog checkers and drivers to force and measure analog signals during the playback simulations. The impact of the tool is not a trivial task to be performed. Indeed, since the previous approach was based on manual checks performed by the engineers, it is not easy to compute the time saved for each check. The metrics that have been considered are related to the impact of the tool over the simulation times and the memory impact. In general, the tool increases the simulation time by about 9% and the memory usage by 2% which is a reasonable impact from the point of view of the tool user.