Implementation of an Approximated FIR Filter on FPGA for Laser Line Extraction from Pixel Data

Approximate computing is an emerging design paradigm that trades in accuracy for resource consumption. Due to the limits of human perception, a certain amount of error is tolerated in most applications that involve the human perception. These include, for instance, image and audio processing. In this master thesis, approximate computing techniques are employed on an image processing pipeline embedded in a 3D scanner that extracts laser line data from a camera sensor with the goal of computing the shape of the object being scanned. To do this, the position of the laser line must be determined. In the pipeline, the data stream is manipulated by FIR filters that first smooth it to reduce noise levels and then transform the light peak generated by the laser (point of maximum intensity) into a zero by performing a derivative on the smoothed data. The location of the zero is estimated by a special unit. Complex circuits such as arithmetic units (e.g., adders, multipliers, and dividers) are good candidates for approximation, as they have a huge impact on the total area and power consumption. Given the complexity of these blocks, their structure is hierarchical and often modular. This, in turn, means that the error can be manipulated at a finer scale by acting on part of the smaller components that make up the circuit. Depending on the kind of approximation one chooses, lower levels (e.g. transistor, logic gates), as well as higher ones (e.g. RTL), can be subject to modifications. The whole design is implemented on FPGA and parameters such as power, area and several types of errors are evaluated. The approximate hardware results are then compared with a software implementation and, subsequently, an exact hardware design. The design space is further explored by acting on parallelism and the filters’ architectures. A set of images taken by a 3D scanner’s camera are used as test vectors.