Design and Verification automation: exploiting Python to ease RTL development

Automating lengthy, repetitive processes where humans could unintentionally make many mistakes is an approach used in many sciences and company applications. It is done in order to save time and consequently also money, without losing quality or even improving it. In the domain of microelectronics and semiconductor, companies are forced to follow tight deadlines in order to meet fast marketing targets. Process automation is crucial to face competitors and have optimal time to market. In this thesis, it will be exposed how it is possible to automate processes for generating digital design for controllers. Also, the automation of verification techniques are handled for achieving high quality and correctness avoiding bug injection. It will be explained how an engine have been developed with \textit{Python} in order to acquire specifications concerning finite state machine through a graphical user interface to ease interaction, starting from introducing all the basic concepts and information required. The application will generate respectively the design and assertions in \textit{SystemVerilog} language. The generated design will follow a very precise and rigorous pattern, that will be described in details, for improving readability and synthesis results. Different categories of Finite State Machine that the engine can manage will be presented, including analysis about results achieved showing timing measurements compared to human effort needed to obtain same goals.