Optimization Techniques for IC Digital Backend: Recovery Methodologies for Power and IR Drop Reduction

Current state-of-the-art integrated circuit complexity induced semiconductor companies to make large investments in Electronic Design Automation. In particular, automation software helps to easily handle design flows and enhances scalability. On the other hand, the optimization strategies embedded in such tools are not effortlessly customizable. In order to achieve the best results in terms of Power, Performance, Area, it is necessary to implement dedicated procedures. This work proposes a specific framework devoted to improving PPA metrics during the timing closure step of the physical design stage. The methodology aims at reducing the drive strength of standard cells while ensuring time constraints are not violated, not to hinder the designed functionality. The physical abstraction is translated into a Linear Program, enabling the exploitation of existing software packages for solving the mathematical problem. Since this framework has been developed to target diverse applications, the described workflow allows the user to specifically address the desired figure of merit. Indeed, in this work, it has been applied to reduce circuit power consumption and IR drop violations. In addition, comparisons with different case studies and parameter choices are presented. Finally, possible future developments are proposed for the further improvement of the performance achievable in this framework.