Implementation of a CNN hardware accelerator based on a reconfigurable spatial array

Convolutional Neural Networks (CNNs) are currently the widely adopted approach to perform computer vision tasks with high accuracy. However, CNNs have a high computational complexity and a high amount of data movement. For this reason, their implementation on general purpose architectures makes not possible to meet latency and energy constraints. Instead, application specific integrated circuits represent an interesting choice for accelerating the filtering operation of the convolution. In this work, a dataflow-based architecture is implemented, which can be reconfigured to support the execution of different convolutional layers. The Spatial Array, based on the Output Stationary (OS) dataflow, performs the computations under different unrolling and interleaving degrees. The Network on Chip (NOC) transfers data from the on-chip global buffer to the RFs of the array and vice versa, as instructions of an Instruction set architecture (ISA). In this way, it is possible to arrange data and to set the type of operations to perform according to the different convolutional layer. Having a reconfigurable hardware structure allows to exploit only the necessary hardware resources and to carry out only the required data movement, making the implementation very efficient for power consumption. To compute the entire convolutional layer, the execution is repeated based on the dimensions of the workload and the available hardware resources. The synthesis and the place and route of the RTL design are performed to evaluate the working frequency and power consumption.