Study and Development of a Radiation-Hardened Implementation of the RISC-V Processor on Reconfigurable Devices

Nowadays, aerospace companies are looking for the best hardware and software solutions that satisfy on one hand their hunger for performance and efficiency and on the other hand solutions require to be verifiable, economical, safe. In this context, RISC-V ISA has emerged as a good candidate capable of meeting these prerequisites, with the addition of being an open source alternative to commercial ISAs. Another prerogative that a design must possess to be used in the field of aerospace is reliability. A reliable system is widely viewed to be a system that tolerates faults; in the aerospace applications faults may occur as consequence of radiations which manifest themselves as Single Effect Upset (SEU). Having at hand a SoC design of a RISC-V implementation for FPGA, the thesis work starts with initial investigation of the RISC-V architecture and how it has been placed into FPGA resources. The interest in the placement arises from the idea that the FPGA design tool does not take into account the field of application of the design and so uses a default directive for the place and route algorithm, leading to potentially critical situations. Once it has been ascertained that the tool returns an implementation that is not robust, next step consisted in the extraction of a salient module for the correct functioning of the processor, as is the ALU, from its RTL description with the aim of make it robust. During the ALU hardening process, consisting in applying the Triple Modular Redundancy (TMR) technique, it has been evaluated how the place and route affects the reliability of the design. In particular, three designs which present differences in terms of placement have been analyzed: the original placement, which is the one proposed by the tool issued by the manufacturer, versus two custom placements. The developed placements aimed to emphasize in one case the isolation among replicas while the other one implements the worst case scenario where replicas share all the physical resources. For each placement, a fault injection campaign was carried out with the purpose of simulating the effect of SEU in the design. In order to test the behavior of the TMR ALU, a test program has been developed with the purpose of stimulate as much as possible all the available functionality of the module. The data collected revealed that the original placement is more prone to failures than the isolated placement and less prone to failures than the worst case. Therefore the isolated design has been taken as reference for additional investigation and optimization. From further injection campaign, performed on sensitive area of the TMR-isolated placement design, it has been possible to observe how the voter which is an essential module for the TMR technique is also the major source of failures, due to the convergence of the nets of the replicas in the same sites. In-depth analyzes showed that although the replicas are positioned far from each other, the convergence of the nets to the voter pushes the tool’s routing algorithm to assign routes such that the nets of a replica are articulated in the area where another replica is arranged. So, isolation at the cell level is not enough but it must also be applied at the routing level. Having this in mind, a basic router has been implemented: it’s able to provide a feasible paths to the design nets that reflect custom constraints, that in this context are to keep the routing within parent replica's area.