Cryogenic FinFETs Modeling and Characterization for Quantum Computing

This study consists in the implementation of a compact model for 14 nm Bulk FinFET tech- nology, from room temperature to low temperature, as well as the characterization of these devices, nFET and pFET. Additionally, to the investigation of di_erent cryogenic models, a correction due to the parasitic resistances has been included. Previous measurements have been exploited to _t the drain current and subthreshold slope models. The drain current model greatly captures the pFET and nFET behaviors, over the full range of temperature. A slight deviation observed at high gate bias on the output characteristic led us to inves- tigate self-heating e_ects. New measurements have been performed in order to gauge the temperature increase due to the operation of the device. FinFETs with di_erent number of _ns, 8 and 64, have been considered to evaluate the inuence of architecture on heat dissipation. At high power, one can expect up to 275 K increase of the channel temperature at 4 K ambient temperature. At low temperature, thermal resistance function of dissipated power exhibits a non-linear trend, which is characteristic of the phonon radiation mecha- nism. In the same way as the current model, the subthreshold slope model shows excellent _ts to the data. The devices exhibit a subthreshold slope saturation under 150 K, to reach a value of 20 mV/dec at 4 K. From the slope model, we extract a band-tail extension of around 6 meV. The comparison of measurements performed at room temperature versus low temperature revealed an impressive enhancement of the ON-state current, for the nFET and pFET, respectively of 4x and 6x, as well as an increase of the transconductance, of 17% and 30%. In addition, both types of devices exhibit a limited threshold shift of 80 mV. These results are promising for the implementation of a low-power qubits controller at cryogenic temperatures.