Implementation of a Convolutional Neural Network Algorithm on FPGA Using High-Level Synthesis

The advancement of silicon technology is revolutionizing the world in terms of processing power. Algorithms and complex mathematical models that require much computing have been made feasible with ease in the last decade. One of such booming algorithms is Convolutional Neural Network (CNN), a field of Artificial Intelligence that can make very complex predictions. However, with high computing complexity comes the drawback of high power consumption for processing, which is a significant concern for some applications. This thesis describes the Field Programmable Gate Array (FPGA) implementation of a CNN algorithm used to predict the location of people indoors using infrared sensors data, an application that benefits from the high prediction power of the CNN but requires a low power implementation of it. The CNN was already trained before with the support of the Keras tool written in Python. In this work's contribution, the weights and the topology were extracted from this Keras model and translated into C++ code. After that, the code was synthesized into Hardware Description Language (HDL) using High-Level Synthesis (HLS) tools, Vitis HLS and Vivado, and was finally implemented and simulated on Xilinx FPGA chips. Furthermore, the HLS tools were used to explore the design space to optimize the design and find the most cost-effective low-power design for power, area, data type, and technology. The design space exploration was performed in terms of processing parallelism, FPGA technology, and data type. A solution for the most sequential circuit was synthesized in parallelism exploration, with the minimum parallelism possible. The degree of parallelism progressively rose with different solutions until the highest degree of parallelism was possible. The latency, power, and total energy solution of each solution were then evaluated. Furthermore, the solution with the lowest energy consumption found was implemented in an FPGA chip of a more advanced technology that could run the algorithm at a higher frequency, assuming that a faster circuit would deliver even lower energy as the iteration time would be smaller. Lastly, the previous solution was implemented with a fixed-point data type, which loses computation precision but wins with lower circuit complexity. The hardware design efficiency was also compared with the implementation of the algorithm in software by running the algorithm and measuring the execution time on two different STM32 microcontrollers, one with a Floating-Point Unit (FPU) and one without. The energy consumption of the software implementation was estimated using the execution time and the current consumption of the microcontrollers on run-mode. The analysis concluded that indeed FPGAs could provide low-power solutions for the implementation of CNNs. Using higher degrees of parallelism for implementing the algorithm in an FPGA can drastically reduce the computation latency, which reduces the total energy consumption for calculation, but up until a certain point. A very parallelized circuit can introduce more active elements inside the FPGA that draws current but does not necessarily speed up the processing. The drawback of high parallelism is that the larger the area used, the larger and more resourceful the FPGA chip should be, increasing the implementation cost.