Study and development of design techniques for 3D integrated circuits

The level of components integration in ICs is no longer able to follow Moore's law. The transistors’ dimension cannot be further reduced due to technological and physical limitations and the 2D architectures are unable to guarantee the required levels of integration. This is a huge obstacle for the silicon industry in which the demand for more and more powerful and performing components has increased exponentially in the last decade, and this trend does not seem to want to change. To solve this issue, new integration strategies have been developed. The 3D IC provides an elegant solution where the construction of the circuit develops on several vertical tiers. The layers are positioned one above the other which allows achieving higher integration density with lower space, compared to classic 2D circuits. Just as the use of skyscrapers allows to rise the number of inhabitants by not increasing the inhabited area, 3D ICs allow to reach very large scale integration without having to count on the reduction of transistors' dismension. The advantages of the 3D ICs are achieved with a price, the interconnections between two tiers are made by TSVs (through-silicon vias) that need to be managed in a proper way to avoiding drastic drop in the performance. Due to their technological characteristics the TSVs have huge size compared to the traditional interconnections and allow slower communication. This implies that the presence of an excessive number of TSVs in a 3D IC can lead to results that are not feasible or with extremely low performance. In this thesis, a Place and Route algorithm is presented which, starting from a traditional 2D circuit, generates its 3D equivalent while satisfying the area constraints. The tier of belonging and the position on it will be defined for each element that makes up the ciruit according to several optimization. The algorithm provides a solution where the number of TSVs required for the interconnections and the wire length of each tier are minimized. In this way, the critical paths and bottlenecks that can negatively affect the performance of the 3D IC are limited. The algorithm is performed on four different circuits in order to understand how the results obtained are affected by the initial conditions.