Advanced High-Level Synthesis strategies for a Logic-in-Memory exploration tool

Nowadays, von Neumann architectures are reaching limitations in performance, due to the differences in terms of technology between the Central Processing Unit (CPU) and the memory: this critical condition is known as von Neumann bottleneck. New computational paradigms are emerging to overcome the problem. Among them, the Logic-in-Memory (LiM) architectures that bring the computations inside the memory itself, minimizing data transfers between the memory and the CPU. Octantis is a High-Level Synthesis tool, introduced in its first version in 2020 and developed within the VLSI Laboratory of Politecnico di Torino, in order to support designers in the exploration and development of LiM architectures. The program generates a Register Transfer Level (RTL) design of a LiM architecture, which implements an input algorithm described through a high-level programming language. The main advantage in its use consists in reducing the effort and time required to design and verify the whole architecture. One of the most important and thrilling parts of a High-Level Synthesis tool is the scheduling algorithm. It computes in which clock cycle an operation must be performed, paying attention to the data dependencies present in the code and to the resource constraints of the target architecture. In this work, different scheduling algorithms have been studied and introduced inside Octantis, based on the System of Difference Constraints (SDC) formulation, in order to manage new and advanced constraints during the synthesis process. Several tests have been conducted to prove the effectiveness of the proposed solutions and the derived results have shown that the synthesized architectures are well optimized according to the input constraints, helping Octantis to explore more customized implementations for an input algorithm.