Design and analysis of clocking structures for pNML technology

For more than 30 years CMOS technology has led the electronic scenario by means of the constant scaling of transistor sizes but according to the International Technology Roadmap of Semiconductors CMOS scaling is now approaching its physical limits and economical limits. In this scenario alternative technologies are studied to overcome the limitations of charge-based technologies. One promising and interesting “Beyond CMOS” technology listed in ITRS is NanoMagnet Logic (NML). This technology offers several advantages: inherent non-volatility, radiation hardness, low power dissipation, ultra-high density data storage and processing giving new possibilities in the design of logic circuits, like the possibility to mix logic and memory in the same device. NML uses single domain nanomagnets for logic computations. The magnetization can be in-plane (iNML) or out-of-plane (or perpendicular, pNML). The only two possible states of the magnetization vector represent the binary logic states “0” and “1” and single-domain nanomagnets interact with magneto-static field coupling to propagate the information. To guarantee this an external magnetic field is applied to the nanomagnet that is used like a signal clock, generated by an on-chip inductor. The goal of this thesis work is to characterize a possible structure based on pNML to extract all the figures of merit and the parameters useful for more complex circuits. A first part describes the NML theory and the state-of-art of the current research giving a glimpse to basic logic gates like NAND and NOR gates whose functionality has already been demonstrated experimentally. The principle of working is explained, highlighting the crucial parameters in the design of this technology. Then in the second part the structure is simulated and optimized through the COMSOL Multiphysics software and the extracted data are studied in MATLAB. Three soft-magnetic cladding materials with different perpendicular magnetic anisotropy (PMA) are compared via parametric analysis and an estimate for power consumption is given in order to make the structure suitable to be used as a model in a “black box” approach for future works. More complex structures are analyzed for more applications. The results show that clocking of pNML devices in the MHz frequency range with on-chip inductors is feasible.