Fabrication and Analysis of a Planar Junctionless Transistor

Modern technology requires smaller transistors every year, the pursuit of miniaturization on the current devices has shown several difficulties such as leakage current and short channel effects, mostly due to the necessary formation of abrupt source/drain junctions in the channels. Among the possible candidates, junctionless transistors offer an interesting solution for these issues. This project aims to analyze the working principles of a junctionless transistor and to provide a fabrication procedure that allows to obtain a similar device in the USN’s MEMS laboratory. This work is part of a broader project, which aims to define and analyze how the junctionless transistor could become in the future the driving technology in electronics. Last year, the project focused mainly on the definition of theoretical tools for the analysis and simulation of these devices (definition of the working properties). This project is focused on the fabrication and optimization of a possible device. These improvements have allowed to obtain a fabrication procedure that significantly reduced the cost of fabrication in terms of necessary resources and machinery for production.