A Decoupled Access-Execute Reconfigurable Systolic Architecture

In the last few years, deep learning algorithms based on neural networks have achieved compelling results in several cognitive tasks, such as computer vision, speech recognition, and natural language processing. Unfortunately, the high accuracy of Deep Neural Networks comes at the cost of enormous memory and computational burden both during the training phase, where the network learns how to perform a task, and during the inference phase, where the model is used on the field. To overcome these challenges and to meet latency and power constraints of various use cases, several domain-specific hardware accelerators have been lately proposed in the literature. While extremely specialized silicon architectures can deliver high performance, reconfigurable hardware platforms, such as FPGAs and CGRAs, allow to customize the accelerator to the specific neural network and to remain up-to-date with the development of new deep learning algorithms. In this work, a reconfigurable decoupled access execute architecture is proposed as a building block to accelerate matrix multiplication, a key operation in deep neural networks. The main design choice behind this architecture is to provide the abstraction of 2D arrays at the ISA level. Reconfigurable decoupled access execute architecture exposes reconfiguration parameters at design-time to allow the user to control the non-functional figures of merits and at compile-time to meet the needs of different workloads. An implementation targeting the Zynq Ultrascale+ MPSoC ZCU104 by Xilinx has been used to assess the figures of merits on a real reconfigurable platform.