Analisi di un riferimento di tensione virtuale basato su un oscillatore controllato in tensione in tecnologia CMOS 65nm = Analysis of a VCO-based virtual voltage reference in 65nm CMOS

Although geometrical scaling has enabled an enhancement in terms of cost, performance, silicon area and power management in digital circuits, the same is not true for analog ICs. For this reason, there is an increasing research interest in new solutions that exploit both digital design-flow and digital techniques to implement analog functions to take advantage of geometrical scaling. In this scenario, a voltage-controlled-oscillator (VCO)-based virtual voltage reference, based on digital processing of the information, is analyzed in this thesis. For this purpose, an integrated VCO in a 65nm technology has been designed and simulated in the Cadence environment, and has been tested over different PVT (Power supply, Temperature and Process) conditions and simulation data have been processed in the MATLAB tool to estimate the performance of a virtual reference structure. Based on this analysis, the main performance benchmarks of a VCO-based virtual reference have been estimated, also discussing the impact of the main design parameters on the virtual reference performance.