Accurate weight mapping in a multi-memristive synaptic unit for in-memory computing applications

In-memory computing using memristive devices is a promising non-von Neumann approach for making energy-efficient deep learning inference hardware. Synaptic units comprising one or more memristive devices organized in a crossbar array configuration are capable of performing the matrix-vector multiply operations in place, by exploiting the Kirchhoff’s circuits laws. In this Thesis, a weight mapping algorithm is designed, in order to efficiently program such a synaptic unit, comprising four phase-change memory (PCM) devices, to target conductance values. To evaluate the programming scheme, a simulator based on the measured programming characteristics of 10,000 PCM devices is developed in a MATLAB environment. It is shown that the synaptic unit can be programmed reliably without significant overhead in programming time or energy compared to a unit comprising a single PCM device, while gaining resilience to device-level non-idealities and yield. The algorithm is experimentally verified on a prototype chip, including a 2x2 crossbar array of multi-PCM unit cells fabricated in the 90nm CMOS technology node. Experimental validation is performed for two different single device designs making up the multi-PCM unit cell, i.e. unprojected and projected devices; the latter showing improved performances thanks to the possibility to decouple the physical mechanism of resistance storage from the information-retrieval process. The matrix-vector multiply operation is verified on the 2x2 crossbar for both PCM designs and the achieved computational accuracy is evaluated, showing comparable performances to a state of the art, low precision digital system. Improved computational accuracy is proven for unit cells with multiple projected devices.