ICs designers frequently employ memory compilers to produce the memory with desired dimensions and configurations rapidly. Memory design methodology in the academic environment is often insufficient: most process design kits (PDKs) does not include a memory compiler. Besides, the customization of memory and cell dimensions and specific peripherals is constrained by these industrial options, and the internal function/layout is commonly inaccessible. Since many different size arrays can be produced (mainly constrained by system data storage need, area, power, and performance), it is practically impossible to have a perfectly tailored bit-cell for the specific system requirements with modern compilers. This project aims to overcome this problem by designing a simple, modular and flexible SRAM memory compiler that uses a 6T-SRAM cell in 180nm TSMC technology with customizable transistor widths: in this way, the system designer can select the desired transistor sizes in the cell, optimized for the system requirements and size of the array.