Generation and evaluation of software programs for delay testing of microprocessors

Generation and evaluation of software programs for delay testing of microprocessors Nowadays, the electronic devices have invaded lots of different fields becoming very important for most of the objects that are used every days. The quality of these electronic devices is directly connected to their dependability, moreover the semiconductor industries are constantly looking for new technologies that allow big improvements in terms of performance. in the last few years, the channel length of a transistor is set to few tens of nanometers, this is the principal cause of the increasing complexity in manufacturing processes, but it allows very high working frequency and dense designs, leading also more frequent physical defects and devices die in less time. For these reasons electronic devices have to be tested deeply and research has studied lots of different models to represent the behaviour of faulty circuit, one of the most precise in reality representation is the path delay fault model. Moreover, the choice of test type needs some clarifications because implies some advantages and disadvantages, in particular the Software Based Self Test is chosen as it is reliable and often used to test VLSI circuit and in particular micro-processors. In this context the actual challenging problem is to find some automatic or systematic methods to generate software programs able to detect path delay faults for sequential circuit. For this purpose there are lots of commercial and academic tools that helps the research work. One of the most important is the Automatic Test Patterns Generator that, having available the hardware description of the device and its fault list, is able to classify faults and to compute input patterns that detect them. Nowadays this tool is too slow for sequential circuit, so it has to be used to generate patterns for the Pseudo Primary inputs at the combinational level, this implies that these patterns have to be translated in software instructions, this results to be the most challenging one of the method. The method described above is obtained by trial and error process built on the benchmark device named Pulpino, it was developed by ETH Zurich and Università di Bologna and was configured to use the \textit{RI5CY} core. The method efficiency is tested in a scientific way, indeed the fault coverage achieved by this system is compared with the ones get by means of programs written using other strategies. The fault coverage is computed using an innovative sequential fault simulator written for academic research. The result obtained is very satisfying, but the entire process would be tested and then generalized for other sequential devices.