Winograd aware Quantized Neural Network accelerator design

Convolutional Neural Networks (CNNs) are widely used in several application fields such as image processing, computer vision and speech recognition. Their high accuracy is obtained at a cost of a huge amount of parameters and so an high memory demand and number of MAC operations. Hardware accelerator are required in order to speed up the inference. Even if GPUs are the main hardware accelerator platforms because of their huge computation capabilities, they are power-greedy devices, not suitable for embedded and mobile applications, where the computational, memory and power resources are limited. Therefore, FPGA based accelerators can be considered which can offer the right trade-off between performance and flexibility limiting the power consumption. Quantization and Tiling techniques can be exploited to reduce the complexity of MACs and to limit the SRAM and DRAM requirements respectively, bringing benefits in energy consumption and/or throughput. Winograd algorithm allows to reduce the number of MAC operations required to perform the convolution and so to speed up the inference. The speedups increase when operating with larger tile size exposing instability in quantized convolution by producing high numerical error resulting in severe degradation of accuracy. The purpose of this thesis is to design a reconfigurable FPGA accelerator exploiting 8-bit quantization and Winograd algorithms (F(2x2,3x3) and F(4x4,3x3)) adopting tiling method to increase the data reuse and reduce the off-chip DRAM accesses limiting the accuracy degradation introduced by the the optimization techniques.