Design of an FPGA-based Testbed for accelerating Error Characterization of Product Codes

Error-correcting codes enable reliable and efficient data communication and storage and have become an indispensable part of information processing systems. Alongside the development of these codes, it is also essential to know how to evaluate their performance efficiently. Fast prototyping of digital communication systems needs efficient tools for the evaluation of the performance of the transmission algorithms. Since the number of parameters in a modern system can be very high the search for an optimal compromise between performance and complexity is not trivial and, simulation is generally the last tool used to perform this task. To avoid software delays inherent in a long simulation, hardware emulation is investigated. For this reason in order to accelerate the study of Product codes this work present a modular FPGA-based testbed. Open-source, modular and parameterized testbed allows researchers rapidly evaluate error correction performance of the target decoder algorithm and collect statistical data essential to exploring algorithmic improvement opportunities. As will be explained later Product codes are parallel concatenated codes often used in optical communication systems for their good error correction performance and high throughput, thanks to their highly parallelizable decoding process. Even if this Testbed is dedicated to the evaluation of this type of Error-correcting codes it is extremely modular, so a good part of this work may be reused also for other types of codes.