RISC-V : an FPGA implementation for general purpose prototyping hardware

The RISCV project began in 2010 at UC Berkely. It set out to provide a flexible, open source instruction set architecture to offer an alternative to proprietary ISAs which require non disclosures agreements and royalties to be used. Currently the RISCV foundation own, maintain and publish intellectual property related to RISCV’s definition. Although it started out in academia the RISCV instruction set architecture has been adopted by numerous companies, such as • SiFive • Codasip • lowRISC and many more. With such strong industrial adoption, RISCV poses itself as a rival to the ARM’s hegemony in the microcontroller world. This study, made in collaboration with Maxim Integrated, aims to integrate general purpose peripherals (such as I2C, SPI, UART, etc...) with an available RISCV IP provided by an internal group. This work is intended to be a feasibility study for the aformentioned core; possible applications for the microcontroller could be • motor control • replace big state machines The methodology followed these steps • RISCV IP RTL study • publicly available toolchain/IDE selection • compiler performance evaluation • peripheral dedicated firmware development • peripherals integration • develop regression environment for RTL validation • CORDIC peripheral development • LINTing of newly developed RTL • synthesis step with Design Compiler The conclusions can be observed in the ”Conclusion” chapter.